Co-design and Reconfigurable Systems




Knowledge of methodologies for co-design of hardware-software systems
Knowledge of techniques for model partitioning of state machines, statecharts and Petri nets
Knowledge of platforms to support reconfigurable computing



Partition of system models into components
VHDL encoding of obtained components expressed in the above referred formalisms
Experimental verification of a system based on FPGA


Non-technical skills
Ability to manage time and meet deadlines
Ability to work in a team and collaborate in a team
Demanding attitude for quality

General characterization





Responsible teacher

Luís Filipe Santos Gomes


Weekly - 4

Total - 56

Teaching language



Available soon


(1) G. De Micheli, R. K. Gupta; “Hardware-Software Co-Design”; Readings in hardware/software co-design; ACADEMIC PRESS; ISBN 1-55860-702-1; 2001

(2) "VHDL for Designers",  Stefan Sjoholm, Lennart Lindh; Prentice Hall, 1997, ISBN 0-13-473414-9

(3) "Statecharts: a visual formalism for complex systems", vol. 8, pp. 231-274; David Harel; Science of Computer Programming 1987

(4) "Petri Nets and Industrial Applications: A Tutorial", Richard Zurawski and MengChu Zhou; IEEE Transactions on Industrial Electronics, Vol.41, no. 6, December 1994, pp. 567-583

(5) Several journal and Conference papers (having lecturers as authors).

Teaching method

Theoretical subjects are offered in lectures, two hours per week in which discussions are promoted, whenever possible, allowing emphasizing different aspects, from conceptual (namely the partition of models within a model-based development methodology), as well as on implementation aspects and technology of digital systems, including hardware description languages ​​(VHDL) and reconfigurable devices platforms (FPGAs).

The lab classes lasting two hours per week, where students undertake mini-projects "from specification to implementation", with increasing degree of autonomy, using professional level computational tools.
Each group receives one working experimentation board (with one FPGA) allowing testing outside the laboratory.

Evaluation method

The evaluation is guaranteed through 1 individual work, supported by one poster and  oral presentation (40%), and conducting two mini-projects in groups of 2 or 3 students (practice) (each 30%).

Each component is graded with two decimal positions.

Subject matter

1 - Motivation for hardware / software co-design and for reconfigurable systems benefits.

2 - Development Methodologies, unified representations, graphical formalisms (state machines, statecharts, Petri nets), and ​​system-level description languages (SystemC), hardware-level (VHDL) and software-level (C / C + +).

3 - Model partition into hardware components and software components and evaluation metrics, co-simulation, co-verification and co-synthesis. Emphasis on state machines, Petri nets and statecharts.

4 - reconfigurable computing platforms, programmable logic devices (CPLDs and FPGAs) and System-on-a-Chip (SoC).

5 - Analysis of GALS - Globally Asynchronous Locally Synchronous systems

6 - Analysis of high-performance applications. Synchronous versus asynchronous implementations.


Programs where the course is taught: