Microelectronics III

Objectives

At the end of this course the students should have solid knowledge of the different kinds of existent ICs and the steps involved in their concept, fabrication and characterization. The student should understand the operation (concerning the elementar devices), advantages and limitations of ICs based on different logic families, namely TTL, MOS and CMOS, as well as in the more recent technologies of TFTs. He should also be able to correctly select the geometric ratios of devices and design the mask layout of simple circuits based on CMOS technology.

General characterization

Code

11046

Credits

6.0

Responsible teacher

Pedro Miguel Cândido Barquinha

Hours

Weekly - 5

Total - 76

Teaching language

Português

Prerequisites

Available soon

Bibliography

- Peter Shepherd , Integrated Circuit Design, Fabrication and Test, McGraw Hill Higher Education (1996). ISBN: 007057278X
- Christopher Saint, Judy Saint, IC Layout Basics: A pratical guide, McGraw-Hill Professional (2001). ISBN: 0071386254
- Randall Geiger, Phillip Allen, Noel Strader, VLSI: design techniques for analog and digital circuits, McGraw-Hill (1990). ISBN: 0071007288
- Douglas Pucknell, Kamran Eshraghian, Basic VLSI Design, Prentice Hall (1994). ISBN: 0130791539
- Eugene Fabricius, Introduction to VLSI design, McGraw-Hill (1990). ISBN: 007100727X
 
- Several recent papers on the application of TFTs to circuits, to be provided during the lectures.

Teaching method

The lectures pretend to explain the fundamental aspects allowing to correctly design ICs, having in mind several efects such as the total occupied area, consumption, parasitic effects, signal propagation delays, among others. These concepts are mostly explored for the most relevant logic families (nMOS and CMOS), but basic aspects for IC design, independent of the selected logic family, are also presented. Furthermore, these concepts are expanded to the most recent TFT technologies. All this information, as well as bibliography to further explore the concepts, is given to the students after each lecture.

The lab classes are perfectly articulated with the thematics explored during the lectures, making use of very complete freeware tools (DSCH and Microwind), which allow to design circuits and masks in an automated or manual way, being possible with a simulation module to observe what are the effects of small design changes on the performance of the circuits.Several requirements regarding the final performance of circuits are established but the students have multiple paths to achieve them,. Hence, a critical analysis of the obtained results is highly desirable, with the students being persuaded to search, based on the theoretical concepts that they have learn, which are the routes to obtain the best possible designs.

Evaluation method

Students are evaluated by two theoretical tests (optional and made in the Moodle) carried out throughout the semester. Students who do not want to, or cannot, make the tests in Moodle, will be able to take an exam that will replace the result of tests.

Marks in Moodle >=15/20 might be taken to an oral examination

Final score:

50 % average tests (Moodle) or exam

50 % - 3 reports on lab works (20 % models, 10 % TCAD, 20 % Microwind)

Final approval with "frequencia" and average of 2 tests or exam >9.5/20.

"Frequencia" implies >9.5 as the average of the 3 lab works reports.

Subject matter

T:

- Integrated circuits (ICs): basic concepts, types of ICs, historical background, generations and current trends

- Design cycle of ICs: main project considerations (technology and architecture, design strategy, power, testing, economics)

- Bolean algebra. Logic gates and main characterization parameters of digital circuits. Comparison of structure and operation of BJTs and MOSFETs in ICs

- Main logic families: TTL, ECL, MOS and CMOS

- nMOS inverter: VTC, passive and active loads, geometric ratio. NOR and NAND gates based on nMOS

- CMOS inverter: VTC, operation and geometric ratio. Latch-up, NOR and NAND gates based on CMOS

- Implementing logic functions with TFTs: limitations and ways to overcome them

- Considerations on CMOS processing and basic concepts for optimizing circuit design

 - Design rules in ICs: hierarquical levels, color codes, stick and symbol diagrams, design rules for mask layout

- Transmission gates in nMOS and CMOS

- Signal propagation delay in nMOS and CMOS gates. Buffer circuits for symetric signal propagation delays

- Considerations about capacitive loads (capacitive loading, logic fan-out delays, distributed drivers, driving off-chip loads, cascaded drivers). Power dissipation in nMOS and CMOS. Noise in digital circuits

 

P:

- Compact models for TFTs (DC operation).

- Physical simulation of TFTs using SILVACO TCAD (Atlas)

- Microwind and DSCH: design of electrical circuits and mask layout. Geometrical efects and capacitve load

Programs

Programs where the course is taught: